1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to phase locked loop circuits.
2. Description of the Related Art
A phase locked loop (PLL) synchronizes an output signal to a reference signal. Phase locked loops are used in a variety of electronic circuits for frequency synthesizing, frequency and phase modulation and demodulation, clock recovery and clock synchronization, among other uses.
FIG. 1a illustrates a basic diagram of a PLL. A phase frequency detector (PFD) 12 receives two signals, FR, a reference signal, and FV, a divided-down version of the output signal. The PFD generates UP and DN (down) signals, indicating whether the frequency of the output signal needs to increase (UP high) or decrease (DN high). The UP and DN signals are input into a loop filter 16. When UP is high and DN is low, VC rises, thereby increasing the frequency of the output of the VCO 18. Similarly, when DN is high and UP is low, VC falls, thereby decreasing the frequency of the output of the VCO 18. In many cases, a divider 20 is used to divide the frequency to a lower frequency by a factor of N; in this case Fout=N*FR.
FIG. 1b illustrates a schematic diagram of a prior art active filter that may be used as the loop filter 16 in the PLL of FIG. 1a. The DN signal from the PFD 12 is coupled to the inverting input of operational amplifier (op-amp) 22, via resistor 24. The UP signal from the PFD 12 is coupled to the non-inverting input of op-amp 22 via resistor 26. The output of op-amp 22 is coupled to its inverting input via capacitor 28 and resistor 30. The non-inverting input is coupled to ground via resistor 32 and capacitor 34.
This type of filter is not often used in integrated applications, mainly because it requires a dual voltage supply and needs two tightly matched filters. Also, since both inverting and non-inverting inputs are driven by the PFD 12, this filter exhibits common mode problems.
FIG. 1c illustrates a schematic of a second active filter that may be used as the loop filter 16 in the PLL of FIG. 1a. The UP signal from the PFD 12 is coupled to the inverting input of operational amplifier (op-amp) 40, via resistor 42. The DN signal from the PFD 12 is coupled to the non-inverting input of op-amp 40 via resistor 44. The output of op-amp 40 is coupled to its inverting input via resistor 46. The non-inverting input of op-amp 40 is coupled to ground via resistor 48. The output of op-amp 40 is coupled to the inverting input of op-amp 50 via resistor 52. The output of op-amp 50 is coupled to its inverting input via capacitor 54 and resistor 56. The non-inverting output is coupled to a DC voltage, VDC.
This design also is not particularly useful for integrated designs, since it requires two op-amps, which results in larger area requirements and higher noise and power consumption. Once again, matching the filters is difficult to achieve optimum performance. Also, op-amp 40 does not present a high impedance state to op-amp 50 and, thus, all of the noise from resistors 42, 46, 44 and 48 and PFD 12, and the DC mismatch between op-amp 40 and the inverting input of op-amp 50 will introduce spurs (feed-through).
A different type of PLL is the charge-pump phase locked loop (CP-PLL). A CP-PLL pumps current in and out of a loop filter in response to detected deviations between the output frequency and the reference frequency. Among other factors, CP-PLLs are considered superior with regard to frequency range and cost. However, these devices may be difficult to integrate onto silicon die, which is highly desirable in many applications.
A basic block diagram of a CP-PLL 58 is shown in FIG. 2. In this design, a phase frequency detector (PFD) 12 receives two signals, FR, a reference signal, and FV, a divided-down version of the output signal. The PFD 12 generates UP and DOWN pulses, indicating whether the frequency of the output signal needs to increase (UP pulsed) or decrease (DOWN pulsed). The UP and DOWN pulses cause a charge pump 14 to either source current into a loop filter 16 or sink current from the loop filter 16. As current is sourced to the loop filter 16, VC rises, thereby increasing the frequency of the output of the VCO 18. Similarly, as the charge pump 14 sinks current from the loop filter 16, VC falls, thereby decreasing the frequency of the output of the VCO 18.
The noise floor of a digital circuit and the noise current of the analog charge pump 14 represent the major noise contributors in a CP-PLL within the PLL bandwidth. In a traditional analog charge pump design used in CP-PLL applications, the noise contributions mainly come directly from the active devices used in the analog charge pump to sink and source current. In order to improve the signal-to-noise ratio, a higher reference current can be used in the charge pump; however, the higher reference current may necessitate a higher capacitor value in the loop filter 16, preventing a possible integration into a silicon die. In addition, mismatches between sink and source devices increase the spurious level that must be filtered out with a lower bandwidth filter (again requiring a larger capacitor) and a consequently longer settling time.
Another critical issue for the traditional charge pump is the need of a complex and low noise biasing circuit and the requirements in terms of supply headroom.
Therefore, a need has arisen for a compact charge-pump phase locked loop with low noise characteristics.